Ferroelectric transistors for low-power NAND flash memory
Article metadata
Article Date: 26 November 2025
Article URL: https://www.nature.com/articles/s41586-025-09793-3
Article Image: (no image provided)
Summary
This Nature paper from Samsung SAIT reports on the design, fabrication and characterisation of ferroelectric field-effect transistors (FeFETs) built with hafnia-based ferroelectric layers for use in NAND flash memory. The team demonstrate gate-stack and channel interlayer engineering that yields unusually large memory windows, enabling multi-level storage (QLC/PLC levels) at lower voltages and with improved retention and disturbance immunity. The work combines detailed experiments, extensive device characterisation (TEM, XRD, SIMS), reliability testing at 25 °C and 85 °C, and TCAD/numerical simulation to explain the device physics — especially the interplay of polarization switching, charge trapping and gate interlayer capacitance. The paper argues that ferroelectric transistors can be a practical route to dense, low-power 3D NAND beyond traditional charge-trap or floating-gate approaches.
Key Points
- The group fabricated hafnia-based FeFET structures integrated into NAND-style device stacks and characterised them with microscopy, XRD and chemical analysis.
- Gate-stack engineering (including thin SiO2 or high-k channel interlayers such as Ta2O5) is essential to control electric fields, suppress undesired charge injection and expand the memory window.
- Devices show large memory windows sufficient for QLC and PLC-level operation and maintain retention and endurance across temperature (25 °C and 85 °C) tests.
- Numerical simulations and a bespoke TCAD/numerical simulator reproduce programming/erase behaviour and link memory-window scaling to gate interlayer capacitance and charge-tunnelling dynamics.
- Extended-data experiments highlight read/disturbance behaviour, pass-disturbance at elevated temperature and the necessity of channel IL to avoid performance degradation.
- Structural analysis indicates a metal stressor promotes the ferroelectric phase in HZO films, while certain IL depositions do not harm HZO crystallinity.
- Comparisons and supplementary tables benchmark the FeFET NAND against charge-trap NAND, illustrating potential advantages in low-power operation and multi-level density.
- The paper is a collaborative Samsung effort with detailed author contributions and open data available on request; peer-review files are linked by the publisher.
Context and relevance
As data-centre energy demand and AI-driven storage needs rise, reducing memory energy per bit and increasing density are priorities. Ferroelectric hafnia (HfO2-based) transistors offer a CMOS-compatible path to lower-voltage, multi-level non-volatile memory. This research addresses key practical hurdles — gate-stack design, charge trapping, field distribution and reliability — that have slowed adoption. For semiconductor engineers, memory architects and device researchers, the work maps out realistic engineering solutions and shows experimentally validated performance at industry-relevant conditions. It ties into broader efforts to scale 3D VNAND and to find BEOL- and CMOS-friendly non-volatile devices for high-density storage and neuromorphic applications.
Author perspective (punchy)
Punchy take: Samsung’s team delivers the kind of engineering detail you actually need if you care about moving ferroelectric NAND from lab curiosity to product-ready memory. They don’t just show big memory windows — they dig into why those windows appear, why channel interlayers matter, and how the stack behaves under real stress. If you work on memory circuits, system power or device integration, the technical depth here is worth your time.
Why should I read this?
Short version: saves you time. If you want a concrete blueprint for making ferroelectric transistors work in NAND — including fabrication notes, reliability data and matching simulations — this paper bundles it all. It’s especially useful if you’re hunting for low-voltage, high-density alternatives to charge-trap NAND or exploring ferroelectric devices for next-gen storage and neuromorphic hardware.