Nvidia-backed photonics startup Ayar Labs eyes hyperscale customers with GUC design collab

Summary

Ayar Labs, backed by Nvidia, has announced a collaboration with Taiwanese design-services company Global Unichip Corp (GUC) to integrate Ayar’s TeraPHY photonic I/O chiplets into GUC’s XPU reference designs. The move aims to replace short-range copper interconnects with co-packaged optical I/O, promising aggregate chip-to-chip bandwidths above 200 Tbps — more than an order of magnitude above today’s fastest interconnects. The partners will validate designs against reference architectures and UCIe chiplet standards (UCIe-S and UCIe-A) to make photonic integration accessible to hyperscalers. Ayar says demonstrations and prototypes exist (including work with Intel and DARPA), but production validation and reliability for TSMC-fabricated parts remain the critical hurdles. The timeline to see optical I/O in volume accelerators is roughly two years, according to Ayar’s CTO.

Key Points

Ayar’s TeraPHY photonic chiplets are designed to be co-packaged with compute dies to enable chip-to-chip optical I/O.
The collaboration with GUC targets XPU reference designs to fast-track hyperscaler adoption via validated design flows.
Optical I/O could deliver >200 Tbps aggregate bandwidth, surpassing current top interconnects (~14.4 Tbps).
Co-packaged optics could let compute domains scale beyond single racks, reducing the need for ultra-dense, high-power racks.
Production reliability is a major risk: a failed optical die could disable an expensive accelerator, so validation is essential.
Initial focus is on multi-chip packages using UCIe-S (package-level) and UCIe-A (die-to-die) standards.
Expect a multi-year road to volume adoption; Ayar predicts maturation within about two years.

Content summary

Ayar Labs and GUC are creating a reference design flow to integrate photonic I/O chiplets into XPU designs for hyperscale customers. By moving from copper to optical links co-packaged with compute dies, the partners claim they can achieve vastly greater bandwidth while keeping power density manageable. The plan addresses architectural, power, signal integrity, mechanical and thermal challenges, and aims to provide hyperscalers with validated IP and reference implementations to avoid reinventing complex photonics integration. Demonstrations exist, but extensive validation for TSMC production and long-term reliability testing are still required before widespread deployment.

Context and relevance

This collaboration sits at the intersection of several industry trends: the push for larger scale-up GPU/accelerator domains, the limits of copper at metre-scale signalling, and the growing chiplet/UCIe ecosystem. Nvidia’s own rack designs have been constrained by copper’s reach and transceiver power costs, prompting interest in co-packaged optics. If Ayar+GUC can deliver reliable, manufacturable photonic I/O, hyperscalers could design accelerators that span aisles or entire halls without exploding rack power density — changing how datacentres are architected and reducing the need for extreme-power racks.

Author style

Punchy — this is a tale of a potential infrastructure leap. For those tracking datacentre scale, chiplet standards and the race to tame AI power, this collaboration could be a real accelerant. Don’t skim if you care about where hyperscale kit will look in two years.

Why should I read this?

Look — optics in chip packages might sound niche, but it could save you from designing or buying another 600kW monstrosity. If you work on hyperscale infrastructure, accelerators, or chiplet-based designs, this is the sort of development that changes where and how you place compute. Quick heads-up: the tech is promising, but manufacturing and reliability are the sticky bits. Worth a five-minute read so you know who’s likely to shake up datacentre topology next.

Source

Source: https://go.theregister.com/feed/www.theregister.com/2025/11/16/ayar_guc_collab/